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  • b2dcf0f7f7d9085128fe097c6d6300128f29b9ba
  • master default protected
  • PCB_V0_9
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Created with Raphaël 2.2.017Oct1129Aug10May3Nov8Dec6310Nov818Oct10Aug613Jul914Jun94231May9Mar816Jan18Dec171630Nov25228Oct26231916141316Sep158742131Aug2814Merge branch 'master' of ssh://gitlab.ost.ch:45022/sciceg/lippunerag/wabesense/datalogger_hardwaremastermasterremoved old copy of pcb_extension. Removed backup zip files. Redesigned current limiterchore: clean up current limiter folderAdded first version of pcb extension to limit current on Sensordoc: fix links in README.rstdoc: fix link to pcb dimensionsdoc: fix README tabledoc: fix linksUpdate .gitlab-ci.yml fileUpdate .gitlab-ci.yml fileUpdate .gitlab-ci.yml fileUpdate .gitlab-ci.ymlremove check link in CI/CD process --> always hang upUpdate .gitlab-ci.yml filecorrected kiCAD linksadded link checker for documentationremove static path from configurationupdated version information about documentation of hardwareadded documentation about ordering process for PCBsupdated readme filechanged theme to sphinxdocimproved io descriptionupdated&extended ioDescriptionupdated pcb dimension pdfpcb dimenstion documentationadded more possible alternate componentsremoved unused STM32L412 datahseet, added new correct datasheetschematic updated to v1_1 (changed only some resistor/capacitor values, changed U2, U5, U6 type with same I/O & package)improved connector J6/J7 --> add orientation in Footprint on fabrication layer, improved silkscreen of them as wellcorrected USB connectorlast PCB design correctionsready for order of v1_0, updated position file of components for automatic assembly, updated BOM with generic parts of assembler companyupdated BOMupdated documentation picturesdesign finishedadded missing step & kicad_mod files (footprint, 3D)DRC free design, last finish pendingall signals routed, DRC check open, finish afterwardsPCB routing is ongoing, changed some critical components (availability) in schematic an design (most of the DC-DC converters, power-switches)updated read-me