Add parser

hdltbgen/__main__.py

@@ -3,6 +3,9 @@
 from pathlib import Path
 from hdltbgen.cli.parser import generate_parser
 from hdltbgen.parser.vhdl import Parser_VHDL
+from hdltbgen.generator.excel import Generator_Excel
+from hdltbgen.generator.vhdl import Generator_VHDL
+from hdltbgen.generator.csv import Generator_CSV
 
 __all__ = ['main']
 
@@ -20,8 +23,58 @@ def main():
     parser = generate_parser()
     args = parser.parse_args()
 
+    print(args)
 
+    # Get the arguments
+    clock = getattr(args, 'clock', [])
+    resetn = getattr(args, 'reset-negative', [])
+    resetp = getattr(args, 'reset-positive', [])
+    file = getattr(args, 'file', "")
+    generator = getattr(args, 'type', "")
+    output = getattr(args, 'output', str(Path(file).parent))
+    vunit = getattr(args, 'vunit', False)
+    simfile = getattr(args, 'simfile', False)
+    ask = getattr(args, 'ask', False)
 
+    if not output:
+        output = Path(file).parent
+    else:
+        output = Path(output)
+
+    # Check if file exists
+    filePath = Path(file)
+    if not filePath.exists():
+        raise FileNotFoundError(f"File {filePath} not found.")
+    
+    # Get file type
+    fileType = filePath.suffix[1:]
+    if fileType == "vhd":
+        parser = Parser_VHDL(filePath, ask)
+        myDict = parser.parse()
+        if clock:
+            myDict.add_clock(clock)
+        if resetn:
+            myDict.add_resetn(resetn)
+        if resetp:
+            myDict.add_resetp(resetp)
+        myDict.auto_add_signals()
+        
+    else:
+        raise ValueError(f"File {filePath} type is not supported (yet).")
+    
+    # Generate testbench
+    for gen in generator:
+        if gen == "vhdl":
+            myGen = Generator_VHDL(output.joinpath(filePath.stem + "_tb.vhd"), myDict, vunit, simfile)
+            myGen.generate()
+        elif gen == "csv":
+            myGen = Generator_CSV(output.joinpath(filePath.stem + "_tb.csv"), myDict, vunit)
+            myGen.generate()
+        elif gen == "excel":
+            myGen = Generator_Excel(output.joinpath(filePath.stem + "_tb.xlsm"), myDict, vunit)
+            myGen.generate()
+        else:
+            raise ValueError(f"Generator {gen} not supported.")
 
 
 if __name__ == '__main__':

hdltbgen/cli/parser.py

@@ -11,9 +11,14 @@ def generate_parser():
     parser = argparse.ArgumentParser(prog=metadata('hdltbgen')['Name'], description=metadata('hdltbgen')['Summary'], formatter_class=argparse.ArgumentDefaultsHelpFormatter)    
 
     # Testbench flow
+    parser.add_argument('-f', '--file', help='Name of the VHDL file', type=str, action='store', required=True)    
+    parser.add_argument('-t', '--type', help='Type of testbench (vhdl, csv, excel) (Multiple types can be provided)', type=str, action='append', required=True)
+    parser.add_argument('-o', '--output', help='Output folder (Default folder of input file)', type=str, action='store', required=False)
     parser.add_argument('-c', '--clock', help='Name of the clock (Multiple clocks can be provided)', type=str, action='append', required=False)
     parser.add_argument('-rn', '--reset-negative', help='Negative reset (Multiple resets can be provided)', type=str, action='append', required=False)
     parser.add_argument('-rp', '--reset-positive', help='Positive reset (Multiple resets can be provided)', type=str, action='append', required=False)   
-    parser.add_argument('-f', '--file', help='Name of the VHDL file', type=str, action='store', required=True)    
+    parser.add_argument('-v', '--vunit', help='Generate VUnit testbench', action='store_true', required=False)
+    parser.add_argument('-s', '--simfile', help='Generate separate sim-top-file', action='store_true', required=False)
+    parser.add_argument('-a', '--ask', help='Ask for values of generics/parameters', action='store_true', required=False)
 
     return parser

hdltbgen/hdldict/hdldict.py

@@ -67,8 +67,7 @@ class hdldict():
         for clk in clocks:
             if not any(port_ele.name == clk for port_ele in self._ports):
                 raise ValueError(f"Clock {clk} not found in the port list.")
-
-        self._clock.append(clocks)
+            self._clock.append(clk)
 
     def add_resetn(self, resetns: list):
         """Add a new resetn.
@@ -83,8 +82,7 @@ class hdldict():
         for rstn in resetns:
             if not any(port_ele.name == rstn for port_ele in self._ports):
                 raise ValueError(f"Resetn {rstn} not found in the port list.")
-
-        self._resetn.append(resetns)
+            self._resetn.append(rstn)
 
     def add_resetp(self, resetps: list):
         """Add a new resetp.
@@ -99,8 +97,7 @@ class hdldict():
         for rstp in resetps:
             if not any(port_ele.name == rstp for port_ele in self._ports):
                 raise ValueError(f"Resetp {rstp} not found in the port list.")
-
-        self._resetp.append(resetps)
+            self._resetp.append(rstp)
 
     @property
     def clock(self) -> list: