Fix errors in parsing and generating of VHDL files

hdltbgen/generator/templates/vhdl.j2

@@ -296,9 +296,9 @@ begin
             {% if not port.name in hdl.clock %}
             {% if port.direction == "out" or port.direction == "inout" %}
             {% if vunit %}
-            check (tb_{{ port.name }}_exp = tb_{{ port.name }}, "Error with {{ port.name }} in test vector " & Integer'image(vectorNr_v) & ". Expected = " & to_string_{{ port.type }}(tb_{{ port.name }}_exp) & ", was = " & to_string_{{ port.type }}(tb_{{ port.name }}), warning);
+            check (tb_{{ port.name }}_exp = tb_{{ port.name }}, "Error with {{ port.name }} in test vector " & Integer'image(vectorNr_v) & ". Expected = " & to_string_{{ port.type_sanitized }}(tb_{{ port.name }}_exp) & ", was = " & to_string_{{ port.type_sanitized }}(tb_{{ port.name }}), warning);
             {% else %}
-            assert tb_{{ port.name }}_exp = tb_{{ port.name }} report "Error with {{ port.name }} in test vector " & Integer'image(vectorNr_v) & ". Expected = " & to_string_{{ port.type }}(tb_{{ port.name }}_exp) & ", was = " & to_string_{{ port.type }}(tb_{{ port.name }}) severity warning;
+            assert tb_{{ port.name }}_exp = tb_{{ port.name }} report "Error with {{ port.name }} in test vector " & Integer'image(vectorNr_v) & ". Expected = " & to_string_{{ port.type_sanitized }}(tb_{{ port.name }}_exp) & ", was = " & to_string_{{ port.type_sanitized }}(tb_{{ port.name }}) severity warning;
             {% endif %}
             {% endif %}
             {% endif %}

hdltbgen/hdldict/hdldict.py

@@ -44,12 +44,12 @@ class hdldict():
                 self._clock.append(port_ele_clk.name)
 
         # try to find a reset in the port list
-        if not self._resetn:
+        if not self._resetn and not self._resetp:
             for port_ele in self._ports:
                 if "rstn" in port_ele.name.lower() or "resetn" in port_ele.name.lower() or "nreset" in port_ele.name.lower() or "nrst" in port_ele.name.lower():
                     self._resetn.append(port_ele.name)
 
-        if not self._resetp:
+        if not self._resetp and not self._resetn:
             for port_ele in self._ports:
                 if "rst" in port_ele.name.lower() or "reset" in port_ele.name.lower() or "rst" in port_ele.name.lower():
                     self._resetp.append(port_ele.name)

hdltbgen/hdldict/hdlport.py

@@ -66,6 +66,20 @@ class hdlport():
         """
         self._direction = value
 
+    @property
+    def type_sanitized(self) -> str:
+        """Base datatype of the port.
+        
+        :return: Base datatype of the port
+        :rtype: str
+        """
+
+        # Check if the type contains () and remove them and everything inside
+        if "(" in self._type:
+            return self._type[:self._type.index("(")]
+        else:
+            return self._type
+
     @property
     def type(self) -> str:
         """Type of the port.

hdltbgen/parser/vhdl.py

@@ -107,7 +107,7 @@ class Parser_VHDL(Parser):
                         myDict.add_param(gen_ele)
 
                     # Check if the line is the last one
-                    if line is None or ");" in line:
+                    if line is None or ");" == line:
                         generic_running = False
                         continue
 
@@ -124,7 +124,7 @@ class Parser_VHDL(Parser):
                         myDict.add_port(port_ele)
 
                     # Check if the line is the last one
-                    if line is None or ");" in line:
+                    if line is None or ");" == line:
                         port_running = False
                         continue