Small fixes in VHDL generation

hdltbgen/__main__.py

@@ -23,7 +23,7 @@ def main():
     parser = generate_parser()
     args = parser.parse_args()
 
-    print(args)
+    #print(args)
 
     # Get the arguments
     clock = getattr(args, 'clock', [])

hdltbgen/generator/templates/vhdl.j2

@@ -157,13 +157,13 @@ architecture tb of {{ hdl.entity_name }}_tb is
     -- This function converts a std_logic value into a string.
     function to_string_std_logic(value : std_logic) return string is -- @suppress
     begin
-        return MVL9_TO_CHAR_C(std_ulogic(value));
+        return std_logic'image(value);
     end function to_string_std_logic;
 
     -- This function converts a std_ulogic value into a string.
     function to_string_std_ulogic(value : std_ulogic) return string is -- @suppress
     begin
-        return MVL9_TO_CHAR_C(value);
+        return std_ulogic'image(value);
     end function to_string_std_ulogic;
 
 begin

hdltbgen/hdldict/hdldict.py

@@ -40,7 +40,7 @@ class hdldict():
                 port_ele_clk.direction = "in"
                 port_ele_clk.type = "std_logic"
                 port_ele_clk.virtual = True
-                self.add_port(port_ele_clk)
+                self.add_port(port_ele_clk, True)
                 self._clock.append(port_ele_clk.name)
 
         # try to find a reset in the port list
@@ -164,12 +164,17 @@ class hdldict():
         """
         return self._params
 
-    def add_port(self, new_port):
+    def add_port(self, new_port, front=False):
         """Add a new port.
 
         :param new_port: New port to add
         :type new_port: hdlport
+        :param front: Add to the front of the list
+        :type front: bool
         """
+        if front:
+            self._ports.insert(0, new_port)
+        else:
             self._ports.append(new_port)
 
     def add_param(self, new_param):