Handles end of VHDL entity parsing

Adds logic to identify and terminate parsing at the end of a VHDL entity declaration. Improves parsing accuracy by ensuring proper detection of the `end entity` statement.

hdltbgen/parser/vhdl.py

@@ -52,6 +52,11 @@ class Parser_VHDL(Parser):
             else:
                 
                 if generic_running == False and port_running == False:
+                    # Identify end entity
+                    end_entity_match = re.match(r"^\s*end\sentity\s+(\w+);", line, re.IGNORECASE)
+                    if end_entity_match:
+                        break
+
                     # Identify generic
                     generic_match = re.match(r"^\s*generic\s*\(", line, re.IGNORECASE)
                     if generic_match: