Skip to content

GitLab

Explore

Sign in

X

XiBIF

Project information

XiBIF - Xilinx Board Interface IP -- Simple bridge between Python and Programmable Logic (PL) in a Xilinx SoC, such as a Zynq-7000.

709 Commits
6 Branches
34 Tags
24 Releases

README
MIT License
GitLab Pages

Created on

November 05, 2020

Loading